Mapping and Scheduling for Circuit-Switched Network-on-Chip Architecture
نویسندگان
چکیده
منابع مشابه
Mapping and Scheduling for Circuit-Switched Network-on-Chip Architecture
© 2009 Chia-Ming Wu et al. 111 Network-on-chip (NoC) architecture provides a highperformance communication infrastructure for systemon-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto ...
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Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores i...
متن کاملapplication mapping onto network-on-chip using bypass links
increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...
متن کاملapplication mapping onto network-on-chip using bypass channel
increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...
متن کاملOn Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion...
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ژورنال
عنوان ژورنال: ETRI Journal
سال: 2009
ISSN: 1225-6463
DOI: 10.4218/etrij.09.0108.0608